The formation of semiconductor devices (which may actually include conductive and insulative materials as well as semiconductive elements) often involves removing amounts of material included as part of the device. Occasionally, the desired result of removing material is a planarized surface. Other times, the desired result is an opening extending at least partway into the material. Examples of both results occur in the manufacture of dynamic random access memory (DRAM) devices, wherein transistor gates are formed over a semiconductor substrate. Once the gates are formed, an insulator can be deposited between and over them. The surface of this insulator is lowered to the general level of the gate top and planarized through etching or CMP. After that, a contact opening is etched through the insulator to a doped region of the semiconductor substrate that forms a transistor source or drain. This opening will subsequently be filled with conductive material, thereby allowing electrical communication with the doped substrate.
This process of forming a hole within an insulation layer and filling that hole with a conductive material is generally known as a damascene process. Damascene processes offer an alternative to etching away undesired portions of a continuous conductive layer and surrounding the remaining portions with insulation. Damascene processes used at various fabrication stages provide additional examples of where material removal is desired in the context of DRAM devices. For example, initially providing the damascene insulation layer may involve CMP before the hole is formed therein, and forming the hole usually involves an etching step.
During CMP or etching steps such as those described above, it is often preferable to provide some sort of CMP stop or etch stop at a location defining the extent of the removal process. Oftentimes this CMP/etch stop will be some sort of material that is more resistant if not completely immune to the CMP/etch process than is the material that is to be removed. For example, U.S. Pat. No. 5,485,035 by Lin et al. discloses using a first boron-doped oxide layer in carrying out a planarizing etch back (see Lin's FIG. 3) and a second boron-doped oxide layer to stop the via etch through an overlying insulating layer (Lin's FIG. 5).
Such oxides can be deposited by growing them from a surface in an oxidizing atmosphere or by conventional deposition methods, such as chemical vapor deposition (CVD). Another method of providing oxide is a process known as FLOWFILL™. The FLOWFILL™ process involves reacting silane with vaporized hydrogen peroxide. The reaction results in a gas which condenses as a liquid on a substrate cooled to about 0° C. A subsequent heat treatment dries the liquid to form SiO2.
As for the application of oxides formed by the FLOWFILL™ process, prior art discloses a CMP process that stops within such a layer, although it is unclear from one particular reference whether this is a matter of properly timing the CMP or due to some property of the oxide itself. See Sabine Penka, Integration Aspects of Flowfill and Spin-on-Glass Process for Sub-0.35 μm Interconnects, PROCEEDINGS OF THE IEEE 1998 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, at 271 (1998). Significantly, this reference further specifies that “Flowfill . . . need[s] to be enclosed by a base and a cap oxide.” Other references further emphasize the presence of a base and cap. See, e.g., U. Höckele, et al., Flowfill-Process as a New Concept for Inter-Metal-Dielectrics, MATERIALS SCIENCE FORUM, at 235 (1998); A. Hass Bar-Ilan et al., A comparative study of sub-micron gap filling and planarization techniques, PROCEEDINGS OF THE SPIE—THE INTERNATIONAL SOCIETY FOR OPTICAL ENGINEERING, at 278–279 (1995); K. Beekmann et al., SUB-MICRON GAP FILL AND IN-SITU PLANARISATION USING FLOWFILL™ TECHNOLOGY, at 137 (1996). The base layer is an oxide provided by plasma-enhanced CVD (PECVD) and serves as an adhesion layer for the oxide formed by the FLOWFILL™ process.
Concerning altering the properties of layers formed by the FLOWFLL™ process, U.S. Pat. No. 5,985,770, also assigned to Micron Technology Inc., discloses gas phase doping of a layer formed by the FLOWFLL™ process before or during the heat treatment that ultimately solidifies the liquid into SiO2 as part of the FLOWFLL™ process.
Given the state of the prior art in terms of CMP and etch stops, there is a constant need in the art to find a new etch stop or CMP stop and new ways of making them. Moreover, there is also a need in the art to find new applications for and modifications of the FLOWFILL™ process.